The present disclosure relates to memory access systems, and more particularly to a technology for detecting a data transfer error occurring when accessing a memory.
In recent memory systems, with increased capacity and higher data processing speed, a double data rate synchronous dynamic random access memory (DDR-SDRAM) has been mainly used. In DDR-SDRAMs, a data signal (DQ) can be transferred in synchronization with both rising and falling edges of a data strove signal (DQS), and thus, data transfer at a data rate that is twice the data rate of conventional SDRAMs is possible.
In the DDR specification, bidirectional data signal and data strobe signal are used as standards, and an operation (a write operation) for transmitting data to a DDR-SDRAM and an operation (a read operation) for receiving data from the DDR-SDRAM are performed. In view of supporting high speed data access, importance is put on optimizing the data strobe signal in both write and read operations. In a read operation, in particular, a data signal and a data strobe signal transmitted from the DDR-SDRAM are substantially in phase with each other, and therefore, it is necessary to generate a data strobe signal out of phase by 90 degree relative to a data signal and find a timing adjustment point where data can be stably latched.
In a write operation, it is necessary to appropriately adjust a timing relationship between a command signal and a clock signal to a memory and a timing relationship with which the data signal is latched using the data strobe signal. On the other hand, in the read operation, it is necessary to appropriately adjust a timing relationship with which the data signal is latched using the data strobe signal. For such timing adjustment, for example, in Japanese Patent Publication No. 2008-210487, a configuration in which a loopback test is performed is described.
FIG. 6 is a diagram illustrating a configuration of a DDR-SDRAM interface circuit described as a conventional example in Japanese Patent Publication No. 2008-210487. A DDR-SDRAM interface circuit 51 of FIG. 6 has a normal operation mode in which a data signal DQ is communicated to a DDR-SDRAM and a test mode in which operation confirmation of the DDR-SDRAM interface circuit 51 itself is performed. When a test control signal TEST becomes high, the DDR-SDRAM interface circuit 51 is turned to a loopback test mode, and a data selector DS selects and outputs pattern data DP which is outputted from a pattern generating circuit 61. In this loopback test, in a data strobe signal input/output section 52, a data strobe signal DQS via an output buffer OB1 is looped back to be received by an input buffer IB1, and in a data signal input/output section 53, a data signal DQ via an output buffer OB2 is looped back to be received by an input buffer IB2. Then, using a data strobe signal DDQS via a DLL circuit 55, the looped-back data signal DQ is captured by a flip-flop FF3 of the data signal input/output section 53. In a determining section 54, whether captured data DQC and the data DP of an output source match each other or not is determined.